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KS8721BL/SL
3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver
Rev. 1.3
General Description
Operating with a 2.5V core to meet low-voltage and lowpower requirements, the KS8721BL and KS8721SL are 10BASE-T/100BASE-TX/FX Physical Layer Transceivers that use MII and RMII interfaces to transmit and receive data. They contain 10BASE-T Physical Medium Attachment (PMA), Physical Medium Dependent (PMD), and Physical Coding Sub-layer (PCS) functions. The KS8721BL/SL also have on-chip 10BASE-T output filtering. This eliminates the need for external filters and allows a single set of line magnetics to be used to meet requirements for both 100BASE-TX and 10BASE-T. The KS8721BL/SL automatically configure themselves for 100 or 10Mbps and full- or half-duplex operation, using an on-chip auto-negotiation algorithm. They are the ideal physical layer transceiver for 100BASE-TX/ 10BASE-T applications.
Features
* Single chip 100BASE-TX/100BASE-FX/10BASE-T physical layer solution * 2.5V CMOS design; 2.5/3.3V tolerance on I/O * 3.3V single power supply with built-in voltage regulator; Power consumption <340mW (including output driver current) * Fully compliant to IEEE 802.3u standard * Supports MII and Reduced MII (RMII) * Supports 10BASE-T, 100BASE-TX, and 100BASE-FX with Far_End_Fault Detection * Supports power-down and power-saving modes * Configurable through MII serial management ports or via external control pins
Functional Diagram
Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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Features (continued)
* Supports auto-negotiation and manual selection for 10/100Mbps speed and full-/half-duplex modes * On-chip, built-in, analog front-end filtering for both 100BASE-TX and 10BASE-T * LED outputs for link, activity, full-/half-duplex, collision, and speed * Supports back-to-back, FX to TX for media converter applications * Supports MDI/MDI-X auto-crossover * KS8721BL is a drop-in replacement for the KS8721BT in the same footprint * KS8721SL is a drop-in replacement for the KS8721B in the same footprint * Commercial Temperature Range: 0oC to +70oC * Industrial Temperature Range: -40oC to +85oC * Available in 48-pin SSOP and LQFP
Ordering Information
Part Number KS8721BL KS8721SL KS8721BLI KSZ8721BL KSZ8721SL KSZ8721BLI KSZ8721SLI Temp. Range 0 C to 70 C 0 C to 70 C -40oC to +85oC 0 C to 70 C 0 C to 70 C -40 C to +85 C -40oC to +85oC
o o o o o o o o o o
Package 48-Pin LQFP 48-Pin SSOP 48-Pin LQFP 48-Pin LQFP 48-Pin SSOP 48-Pin LQFP 48-Pin SSOP
Lead Finish Standard Standard Standard Lead-Free Lead-Free Lead-Free Lead-Free
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Revision History
Revision 0.9 1.0 Date 01/12/04 03/06/04 Summary of Changes Data sheet created. Initial release. Change to new format. Added part-ordering information. Editorial changes on pin description, RMII, and media converter operation. Update circuit design, reset timing, thermal resistance, electrical characteristics, and strapping option circuit. Added BLI product information. MDIO Pull-up resistor value changed to 4.7k. Added note on strapping option pins. Updated bits 1b.0 - 1b.7 to self clearing. Updated electrical characteristics. Updated reference schematic for strapping option configuration to 3.3V. Crystal spec updated to 40 series resistance. Added additional magnetics to qualified transformer table. Added 2 lead-free part options. Added recommended reset circuit. Update ordering information.
1.1 1.2
05/17/04 01/21/05
1.3
06/25/09
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Contents
Pin Configuration .............................................................................................................................................................. 6 Pin Description .................................................................................................................................................................. 7 Strapping Options(1) ........................................................................................................................................................ 10 Functional Description ................................................................................................................................................... 11 100BASE-TX Transmit.................................................................................................................................................. 11 100BASE-TX Receive................................................................................................................................................... 11 PLL Clock Synthesizer.................................................................................................................................................. 11 Scrambler/De-scrambler (100BASE-TX only) .............................................................................................................. 11 10BASE-T Transmit ...................................................................................................................................................... 11 10BASE-T Receive ....................................................................................................................................................... 11 SQE and Jabber Function (10BASE-T only) ................................................................................................................ 12 Auto-Negotiation ........................................................................................................................................................... 12 MII Management Interface ............................................................................................................................................ 12 MII Data Interface ......................................................................................................................................................... 12 Transmit Clock (TXC)........................................................................................................................................... 12 Receive Clock (RXC) ........................................................................................................................................... 12 Transmit Enable ................................................................................................................................................... 13 Receive Data Valid............................................................................................................................................... 13 Error Signals......................................................................................................................................................... 13 Carrier Sense (CRS) ............................................................................................................................................ 13 Collision................................................................................................................................................................ 13 RMII (Reduced MII) Data Interface............................................................................................................................... 13 RMII Signal Definition ................................................................................................................................................... 13 Reference Clock (REF_CLK)........................................................................................................................................ 14 Carrier Sense/Receive Data Valid (CRS_DV) .............................................................................................................. 14 Receive Data [1:0] (RXD[1:0]) ...................................................................................................................................... 14 Transmit Enable (TX_EN)............................................................................................................................................. 14 Transmit Data [1:0] (TXD[1:0])...................................................................................................................................... 14 Collision Detection ........................................................................................................................................................ 14 RX_ER .......................................................................................................................................................................... 14 RMII AC Characteristics................................................................................................................................................ 15 Unused RMII Pins ......................................................................................................................................................... 15 Auto-Crossover (Auto-MDI/MDI-X) ............................................................................................................................... 15 Power Management...................................................................................................................................................... 16 100BT FX Mode............................................................................................................................................................ 16 Media Converter Operation........................................................................................................................................... 17 Circuit Design Reference for Power Supply ................................................................................................................. 18 Register Map.................................................................................................................................................................... 19 Register 0h - Basic Control ........................................................................................................................................... 19 Register 1h - Basic Status ............................................................................................................................................ 19 Register 2h - PHY Identifier 1 ....................................................................................................................................... 20 Register 3h - PHY Identifier 2 ....................................................................................................................................... 20 Register 4h - Auto-Negotiation Advertisement ............................................................................................................. 20 Register 5h - Auto-Negotiation Link Partner Ability ...................................................................................................... 21 Register 6h - Auto-Negotiation Expansion.................................................................................................................... 21 Register 7h - Auto-Negotiation Next Page.................................................................................................................... 21 Register 8h - Link Partner Next Page Ability ................................................................................................................ 22 Register 15h - RXER Counter....................................................................................................................................... 22 Register 1bh - Interrupt Control/Status Register .......................................................................................................... 22 Register 1fh - 100BASE-TX PHY Controller................................................................................................................. 23 Absolute Maximum Ratings(1) ........................................................................................................................................ 24 Operating Ratings(2) ........................................................................................................................................................ 24 Electrical Characteristics(4) ............................................................................................................................................ 24 June 2009 4
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Timing Diagrams ............................................................................................................................................................. 26 Selection of Isolation Transformers(1) ........................................................................................................................... 33 Selection of Reference Crystal ...................................................................................................................................... 33 Package Information ....................................................................................................................................................... 34
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Pin Configuration
MDIO 1 MDC 2 R3D3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 3 4 5 6 48 RST# 47 VDDPLL 46 XI 45 XO 44 GND 43 GND 42 VDDTX 41 TX+ 40 TX39 GND 38 VDDRCV 37 REXT 36 GND 35 GND 34 FXSD/FXEN 33 RX+ 32 RX31 VDDRX 30 PD# 29 LED3/NWAYEN 28 LED2/DUPLEX 27 LED1/SPD100 26 LED0/TEST 25 INT#/PHYAD0
VDDIO 7 GND 8 RXDV/PCS_LPBK 9 RXC 10 RXER/ISO 11 GND 12 VDDC 13 TXER 14 TXC/REF_CLK 15 TXEN 16 TXD0 17 TXD1 18 TXD2 19 TXD3 20 COL/RMII 21 CRS/RMII_BTB 22 GND 23 VDDIO 24
RST# VDDPLL X1 X0 GND GND VDDTX TX+ Tx- GND VDDRCV REXT
MDIO MDC RXD1/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 VDDIO GND RXDV/PCS_LPBK RXC RXER/ISO GND
GND GND FXSD/FXEN RX+ RX- VDDRX PD# LED3/NWAYEN LED2/DUPLEX LED1/SPD100 LED0/TEST INT#/PHYAD0
48-Pin SSOP (SM)
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VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB GND VDDIO
48-Pin LQFP (LQ)
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Pin Description
Pin Number 1 2 3 Pin Name MDIO MDC RXD3/ PHYAD Type(1) I/O I Ipd/O Pin Function Management Independent Interface (MII) Data I/O. This pin requires an external 4.7K pull-up resistor. MII Clock Input. This pin is synchronous to the MDIO. MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK. When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See "Strapping Options" section for details. MII Receive Data Output. During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See "Strapping Options" section for details. MII Receive Data Output. During reset, the pull-up/pull-down value is latched as PHYADDR[3]. See "Strapping Options" section for details. MII Receive Data Output. During reset, the pull-up/pull-down value is latched as PHYADDR[4]. See "Strapping Options" section for details. Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage regulator. See "Circuit Design Ref. for Power Supply" section for details. Ground. MII Receive Data Valid Output. During reset, the pull-up/pull-down value is latched as PCS_LPBK. See "Strapping Options" section for details. MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps. MII Receive Error Output. During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See "Strapping Options" section for details. Ground. Digital core 2.5V only power supply. See "Circuit Design Ref. for Power Supply" section for details. MII Transmit Error Input. MII Transmit Clock Output. Input for crystal or an external 50MHz clock. When REFCLK pin is used for REF clock interface, pull up XI to VDDPLL 2.5V via 10k resistor and leave XO pin unconnected. MII Transmit Enable Input. MII Transmit Data Input. MII Transmit Data Input. MII Transmit Data Input. MII Transmit Data Input. MII Collision Detect Output. During reset, the pull-up/pull-down value is latched as RMII select. See "Strapping Options" section for details. MII Carrier Sense Output. During reset, the pull-up/pull-down value is latched as RMII back-to-back mode when RMII mode is selected. See "Strapping Options" section for details. Ground.
4
RXD2/ PHYAD2 RXD1/ PHYAD3 RXD0/ PHYAD4 VDDIO GND RXDV/ CRSDV/ PCS_LPBK RXC RXER/ISO
Ipd/O
5
Ipd/O
6
Ipd/O
7 8 9
P Gnd Ipd/O
10 11
O Ipd/O
12 13 14 15
GND VDDC TXER TXC/ REFCLK TXEN TXD0 TXD1 TXD2 TXD3 COL/ RMII CRS/ RMII_BTB GND
Gnd P Ipd I/O
16 17 18 19 20 21
Ipd Ipd Ipd Ipd Ipd Ipd/O
22
Ipd/O
23
Gnd
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Pin Number 24 25 26 Pin Name VDDIO INT#/ PHYAD0 LED0/ TEST Type(1) P Ipu/O Ipu/O Pin Function
KS8721BL/SL
Digital IO 2.5/3.3V tolerant power supply. 3.3V power input of voltage regulator. See "Circuit Design Ref. for Power Supply" section for details. Management Interface (MII) Interrupt Out. Interrupt level set by Register 1f, bit 9. During reset, latched as PHYAD[0]. See "Strapping Options" section for details. Link/Activity LED Output. The external pull-down enable test mode and only used for the factory test. Active low. Link/Act No Link Link Act Pin State H L - LED Definition PHYAD0 "Off" "On" "Toggle"
27
LED1/ SPD100/ nFEF
Ipu/O
Speed LED Output. Latched as SPEED (Register 0, bit 13) during power-up/ reset. See "Strapping Options" section for details. Active low. Speed 10BT 100BT Pin State H L LED Definition "Off" "On"
28
LED2
Ipu/O
Full-duplex LED Output. Latched as DUPLEX (register 0h, bit 8) during power-up/ reset. See "Strapping DUPLEX Options" section for details. Active low. Duplex Half Full Pin State H L LED Definition "Off" "On"
29
LED3/ NWAYEN
Ipu/O
Collision LED Output. Latched as ANEG_EN (register 0h, bit 12) during power-up/ reset. See "Strapping Options" section for details. Collision No Collision Collision Pin State H L LED Definition "Off" "On"
30 31 32 33 34 35 36 37 38 39 40 41 42 43
PD# VDDRX RXRX+ FXSD/ FXEN GND GND REXT VDDRCV GND TXTX+ VDDTX GND
Ipu P I I Ipd/O Gnd Gnd I P Gnd O O P Gnd
Power Down. 1 = Normal operation, 0 = Power-down. Active low. Analog 2.5V power supply. See "Circuit Design Ref. for Power Supply" section for details. Receive Input. Differential receive input pins for 100FX, 100BASE-TX, or 10BASE-T. Receive Input: Differential receive input pin for 100FX, 100BASE-TX, or 10BASE-T. Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The default is "0". See "100BT FX Mode" section for more details. Ground. Ground. External resistor (6.49kW ) connects to REXT and GND. Analog 2.5V power supply. 2.5V power output of voltage regulator. See "Circuit Design Ref. for Power Supply" section for details. Ground. Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T. Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T. Transmitter 2.5V power supply. See "Circuit Design Ref. for Power Supply" section for details. Ground.
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Pin Number 44 45 46 47 48
Note: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. Ipd = Input with internal pull-down. Ipu = Input with internal pull-up. Ipd/O = Input with internal pull-down during reset; output pin otherwise. Ipu/O = Input with internal pull-up during reset; output pin otherwise.
KS8721BL/SL
Pin Name GND XO XI VDDPLL RST# Type(1) Gnd O I P Ipu Pin Function Ground. XTAL feedback: Used with XI for Xtal application. Crystal Oscillator Input: Input for a crystal or an external 25MHz clock. If an oscillator is used, XI connects to a 3.3V tolerant oscillator, and X2 is a no-connect. Analog PLL 2.5V power supply. See "Circuit Design Ref. for Power Supply" section for details. Chip Reset. Active low, minimum of 50s pulse is required.
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Strapping Options(1)
Pin Number 6, 5, 4, 3 25 9(3) 11(3) 21(3) 22(3) 27 Pin Name PHYAD[4:1]/ RXD[0:3] PHYAD0/ INT# PCS_LPBK/ RXDV ISO/RXER RMII/COL RMII_BTB CRS SPD100/ No FEF/ Type(2) Ipd/O Ipu/O Ipd/O Ipd/O Ipd/O Ipd/O Ipu/O Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable. Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable. Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable. Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable, PU = Enable. Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default) = 100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as LED1 the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0 means no Far_End _Fault.) Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU (default) = Full-duplex. If Duplex is pulled up during reset, this pin is also latched as the Duplex support in register 4h. Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation. Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode. Pin Function PHY Address latched at power-up/reset. The default PHY address is 00001.
28
DUPLEX/ LED2 NWAYEN/ LED3 PD#
Ipu/O
29 30
Notes: 1. 2.
Ipu/O Ipu
Strap-in is latched during power-up or reset. Ipu = Input with internal pull-up. Ipd/O = Input with internal pull-down during reset; output pin otherwise. Ipu/O = Input with internal pull-up during reset; output pin otherwise. See "Reference Circuit" section for pull-up/pull-down and float information.
3.
Some devices may drive MII pins that are designated as output (PHY) on power-up, resulting in incorrect strapping values latched at reset. It is recommended that an external pull-down via 1k resistor be used in these applications to augment the 8721's internal pull-down.
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Functional Description
100BASE-TX Transmit The 100BASE-TX transmit function performs parallel to serial conversion, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission. The circuitry starts with a parallel to serial conversion that converts the 25MHz, 4-bit nibbles into a 125MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.49k resistor for the 1:1 transformer ratio. Its typical rise/fall time of 4ns complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASET output driver is also incorporated into the 100BASE-TX driver. 100BASE-TX Receive The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self-adjust for environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effects of base line wander and improve dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized 25MHz RXC is generated so that the 4B nibbles are clocked out at the negative edge of RCK25 and is valid for the receiver at the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25MHz reference clock and both TXC and RXC clocks continue to run. PLL Clock Synthesizer The KS8721BL/SL generates 125MHz, 25MHz, and 20MHz clocks for system timing. An internal crystal oscillator circuit provides the reference clock for the synthesizer. Scrambler/De-scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce electromagnetic interference (EMI) and baseline wander. 10BASE-T Transmit When TXEN (transmit enable) goes high, data encoding and transmission begins. The KS8721BL/SL continues to encode and transmit data as long as TXEN remains high. The data transmission ends when TXEN goes low. The last transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with typical 2.5V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by all-ones, Manchester-encoded signal. 10BASE-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent noise at the RX+ or RX- input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8721BL/SL decodes a data frame. This activates the carrier sense (CRS) and RXDV signals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in between data reception.
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SQE and Jabber Function (10BASE-T only) In 10BASE-T operation, a short pulse is put out on the COL pin after each packet is transmitted. This is required as a test of the 10BASE-T transmit/receive path and is called an SQE test. The 10BASE-T transmitter is disabled and COL goes high if TXEN is high for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BASE-T transmitter is re-enabled and COL goes low. Auto-Negotiation The KS8721BL/SL performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its link partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in either full- or half-duplex mode (please refer to "Auto-Negotiation"). Auto-negotiation is disabled in the FX mode. During auto-negotiation, the contents of Register 4, coded in fast link pulse (FLP), are sent to its link partner under the conditions of power-on, link-loss, or restart. At the same time, the KS8721BL/SL monitors incoming data to determine its mode of operation. The parallel detection circuit is enabled as soon as either 10BASE-T normal link pulse (NLP) or 100BASE-TX idle is detected. The operation mode is configured based on the following priority: Priority 1: 100BASE-TX, full-duplex Priority 2: 100BASE-TX, half-duplex Priority 3: 10BASE-T, full-duplex Priority 4: 10BASE-T, half-duplex When the KS8721BL/SL receives a burst of FLP from its link partner with three identical link code words (ignoring acknowledge bit), it will store these code words in Register 5 and wait for the next three identical code words. Once the KS8721BL/SL detects the second code words, it then configures itself according to the above-mentioned priority. In addition, the KS8721BL/SL also checks for 100BASE-TX idle or 10BASE-T NLP symbols. If either is detected, the KS8721BL/SL automatically configures to match the detected operating speed. MII Management Interface The KS8721BL/SL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KS8721BL/SL. The MDIO interface consists of the following: * * A physical connection including a data line (MDIO), a clock line (MDC), and an optional interrupt line (INTRPT). A specific protocol that runs across the above-mentioned physical connection that allows one controller to communicate with multiple KS8721BL/SL devices. Each KS8721BL/SL is assigned an MII address between 0 and 31 by the PHYAD inputs.
An internal addressable set of fourteen 16-bit MDIO registers. Registers [0:6] are required and their functions are specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality. The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status change on the KS8721BL/SL based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh. MII Data Interface The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Controller (MAC) to the KS8721BL/SL, and for receiving data from the line. Normal data transmission is implemented in 4B nibble mode (4-bit wide nibbles). Transmit Clock (TXC) The transmit clock is normally generated by the KS8721BL/SL from an external 25MHz reference source at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KS8721BL/SL normally samples these signals on the rising edge of the TXC. Receive Clock (RXC) For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes down, and autonegotiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BASE-T links, the June 2009 12
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receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle. The KS8721BL/SL synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge of the clock with 10ns setup and hold times. Transmit Enable The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after the last bit of the packet. Receive Data Valid The KS8721BL/SL asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine timing changes in the following way: * For 100BASE-TX links with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the data packet. * For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD "5D" and remains asserted until the end of the packet. Error Signals Whenever the KS8721BL/SL receives an error symbol from the network, it asserts RXER and drives "1110" (4B) on the RXD pins. When the MAC asserts TXER, the KS8721BL/SL will drive "H" symbols (a Transmit Error defined in the IEEE 802.3 4B/5B code group) out on the line to force signaling errors. Carrier Sense (CRS) For 100BASE-TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS). An end-of-stream delimiter, or /T/R symbol pair, causes de-assertion of CRS. The PMA layer will also de-assert CRS if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is deasserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. Collision Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721BL/SL asserts its collision signal, which is asynchronous to any clock. RMII (Reduced MII) Data Interface RMII interface specifies a low-pin count, Reduced Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2]. This interface has the following characteristics: * * * * It is capable of supporting 10Mbps and 100Mbps data rates. A single clock reference is sourced from the MAC to PHY (or from an external source). It provides independent 2-bit wide (di-bit) transmit and receive data paths. It uses TTL signal levels compatible with common digital CMOS ASIC processes.
RMII Signal Definition
Signal Name REF_CLK CRS_DV RXD[1:0] TX_EN TXD[1:0] RX_ER Direction (w/respect to the PHY) Input Output Output Input Input Output Direction (w/respect to the MAC) Input or Output Input Input Output Output Input (Not Required) Use Synchronous clock reference for receive, transmit and control interface Carrier Sense/Receive Data Valid Receive Data Transmit Enable Transmit Data Receive Error
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Reference Clock (REF_CLK) REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device. Each PHY device must have an input corresponding to this clock but may use a single clock input for multiple PHYs implemented on a single IC. Carrier Sense/Receive Data Valid (CRS_DV) CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 noncontiguous zeroes in 10 bits are detected, the carrier is detected. Loss-of-carrier results in the de-assertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV remains continuously asserted from the first recovered di-bit of the frame through the final recovered di-bit and is negated prior to the first REF_CLK that follows the final di-bit. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] remains as "00" until proper receive signal decoding takes place (see "Definition of RXD[1:0] Behavior"). Receive Data [1:0] (RXD[1:0]) RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions), a predetermined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as "00" to indicate idle when CRS_DV is de-asserted. Values of RXD[1:0] other than "00" when CRS_DV is de-asserted are reserved for outof-band signaling (to be defined). Values other than "00" on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC/repeater. Upon assertion of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes place. Transmit Enable (TX_EN) Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN is asserted synchronously with the first nibble of the preamble and remains asserted while all transmitted di-bits are presented to the RMII. TX_EN is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transitions synchronously with respect to REF_CLK. Transmit Data [1:0] (TXD[1:0]) Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] remains as "00" to indicate idle when TX_EN is de-asserted. Values of TXD[1:0] other than "00" when TX_EN is de-asserted are reserved for out-of-band signaling (to be defined). Values other than "00" on TXD[1:0] while TX_EN is de-asserted are ignored by the PHY. Collision Detection Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC reliably re-generates the COL signal of the MII by ANDing TX_EN and CRS_DV. During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a self-test. The Signal Quality Error (SQE) function is not supported by the reduced MII due to the lack of the COL signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required. RX_ER The PHY provides RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 2411- Receive State Diagram). RX_ER is asserted for one or more REF_CLK periods to indicate that an error (e.g., a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) is detected somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the MAC.
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Symbol Parameter REF_CLK Frequency REF_CLK Duty Cycle tSU tH TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK Rising Edge 35 4 2 Min Typ 50
KS8721BL/SL
Max 65
Units MHz % ns ns
Unused RMII Pins Input Pins TXD[2:3] and TXER are pull-down to GND. Output Pins RXD[2:3] and RXC are no connect. Note that the RMII pin needs to be pulled up to enable RMII mode. Auto-Crossover (Auto-MDI/MDI-X) Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The assignment of pinouts for a 10/100 BASE-T crossover function cable is shown below. This feature eliminates the confusion in applications by allowing the use of both straight and crossover cables. This feature is controlled by register 1f:13. See "Register 1fh-100BASE-TX PHY Controller" section for details.
10/100 BASE-T Media Dependent Interface 10/100 BASE-T Media Dependent Interface
Transmit Pair
Receive Pair
Receive Pair
Transmit Pair
Modular Connector (RJ45) NIC
Modular Connector (RJ45) HUB (Repeater or Switch)
Figure 1. Straight Through Cable
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10/100 BASE-T Media Dependent Interface
Receive Pair
KS8721BL/SL
10/100 BASE-T Media Dependent Interface
Receive Pair
Transmit Pair
Transmit Pair
Modular Connector (RJ45) HUB (Repeater or Switch)
Modular Connector (RJ45) HUB (Repeater or Switch)
Figure 2. Crossover Cable
Power Management The KS8721BL/SL offers the following modes for power management: * * Power-Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# low. Power-Saving Mode: This mode can be disabled by writing to Register 1fh.10. The KS8721BL/SL turns off everything except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the KS8721BL/SL shuts down most of the internal circuits to save power if there is no link. Power-saving mode is in the most effective state when auto-negotiation mode is enabled.
100BT FX Mode Please contact your local field application engineer (FAE) for a reference schematic on fiber connection. 100BT FX mode is activated when FXSD/FXEN is higher than 0.6V (this pin has a default pull down). Under this mode, the auto-negotiation and auto-MDI-X features are disabled. In fiber operation, the FXSD pin should connect to the signal detect (SD) output of the fiber module. The internal threshold of FXSD is around 1/2 VDD 50mV (1.25V 0.05V). Above this level, the fiber signal is considered detected. The operation is summarized in the following table:
FXSD/FXEN Less than 0.6V Less than 1.25V, but greater than 0.6V Greater than 1.25 Condition 100TX mode FX mode No signal detected FEF generated FX mode Signal detected Table 1. 100BT FX Mode
To ensure proper operation, the swing of fiber module SD should cover the threshold variation. A resistive voltage divider is recommended to adjust the SD voltage range. Far End Fault (FEF), repetition of a special pattern which consists of 84-one and 1-zero, is generated under "FX mode with no signal detected." The purpose of FEF is to notify the sender of a faulty link. When receiving an FEF, the LINK will go down to indicate a fault, even with fiber signal detected. The transmitter is not affected by receiving an FEF and June 2009 16
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still sends out its normal transmit pattern from MAC. FEF can be disabled by strapping pin 27 low. Refer to the "Strapping Options" section. Media Converter Operation The KS8721BL/SL is capable of performing media conversion with two parts in a back-to-back RMII loop-back mode as indicated in the diagram. Both parts are in RMII mode and with RMII BTB asserted (pins 21 and 22 strapped high). One part is operating in TX mode and the other is operating in FX mode. Both parts can share a common 50MHz oscillator. Under this operation, auto-negotiation on the TX side prohibits 10BASE-T link-up. Additional options can be implemented under this operation. Disable the transmitter and set it at tri-state by controlling the high TXD2 pin. In order to do this, RXD2 and TXD2 pins need to be connected via inverter. When TXD2 pin is high in both the copper and fiber operation, it is disabled transmit. Meanwhile, the RXD2 pin on the copper side serves as the energy detect and can indicate if a line signal is detected. TXD3 should be tied low and RXD3 let float. Please contact your Micrel FAE for a media converter reference design.
VCC
Rx +/-
21 22 Pin
RxD TxD
KS8721BL/SL
Tx +/-
TxC/ Ref_CLK
OSC
FTx
TxC/ Ref_CLK
50MHz
KS8721BL/SL
FR x (Fiber Mode) Pin 34 Pin 21 22
TxD RxD
To the SD pin of the Fiber Module
VCC
Figure 3. Fiber Module
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Circuit Design Reference for Power Supply Micrel's integrated built-in, voltage regulator technology and thoughtful implementation allows the user to save BOM cost on both existing and future designs with the use of the new KS8721BL/SL single supply, single port 10/100 Ethernet PHY.
Ferrite Bead +3.3V +2.5V 10F
13
Ferrite Bead +2.5VA 10F
47
+2.5VPLL 10F 10F
10F
42 31 38
10F
VDDTX
VDDC
VDDPLL
7
VDDI/O IN Voltage Regulator GND KS8721BL/SL
8 12 23 35 36 39 43 44
OUT
24
VDDI/O
Figure 4. Circuit Design
The circuit design in Figure 4 shows the power connections for the power supply: the 3.3V to VDDI/O is the only input power source and the 2.5V at VDDRCV, pin 38, is the output of the voltage regulator that needs to supply through the rest of the 2.5V VDD pins via the 2.5V power plane. The 2.5V VDD pins make the drop-in replacement with the existing KS8721B/BT part. Table 2 shows the drop-in replacement from the existing KS8721B/BT to the KS8721SL/BL. Please contact your local Micrel FAE for Application Note AN-117, "Drop-in Replacement with KS8721BT."
2.5V/3.3V Supply Part Number KS8721B KS8721BT KS8721BI Package 48-SSOP 48-TQFP 48-SSOP 3.3V Supply with Built-in Regulator Part Number KS8721SL KS8721BL KS8721SLI Package 48-SSOP 48-LQFP 48-SSOP
Table 2. Drop-In Replacement
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VDDRCV
VDDRX
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Register Map
Register No. 0h 1h 2h 3h 4h 5h 6h 7h 8h 15h 1bh 1fh Description Basic Control Register Basic Status Register PHY Identifier I PHY Identifier II Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Link Partner Next Page Ability RXER Counter Register Interrupt Control/Status Register 100BASE-TX PHY Control Register
Address 0.15 0.14 0.13
Name Reset Loop-Back Speed Select (LSB)
Description 1 = software reset. Bit is self-clearing 1 = loop-back mode 0 = normal operation 1 = 100Mbps 0 = 10Mbps Ignored if Auto-Negotiation is enabled (0.12 = 1) 1 = enable auto-negotiation process (override 0.13 and 0.8) 0 = disable auto-negotiation process 1 = power-down mode 0 = normal operation 1 = electrical isolation of PHY from MII and TX+/TX0 = normal operation 1 = restart auto-negotiation process 0 = normal operation. Bit is self-clearing 1 = full-duplex 0 = half-duplex 1 = enable COL test 0 = disable COL test 0 = enable transmitter 1 = disable transmitter 1 = T4 capable 0 = not T4 capable 1 = capable of 100BASE-X full-duplex 0 = not capable of 100BASE-X full-duplex
Default(1) RW/SC RW RW
Mode 0 0 Set by SPD100 Set by NWAYEN 0 Set by ISO 0 Set by DUPLEX 0 0 0
Register 0h - Basic Control
0.12 0.11 0.10 0.9 0.8 0.7 0.6:1 0.0
Auto-Negotiation Enable Power Down Isolate Restart Auto-Negotiation Duplex Mode Collision Test Reserved Disable Transmitter 100BASE-T4 100BASE-TX Full-Duplex
RW RW RW RW/SC RW RW RO RW
Register 1h - Basic Status 1.15 1.14 RO RO 0 1
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Address 1.13 1.12 1.11 1.10:7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 2.15:0 Name 100BASE-TX Half-Duplex 10BASE-T Full-Duplex 10BASE-T Half-Duplex Reserved No Preamble Auto-Negotiation Complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability PHY ID Number 1 = preamble suppression 0 = normal preamble 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 1 = remote fault 0 = no remote fault 1 = capable to perform auto-negotiation 0 = unable to perform auto-negotiation 1 = link is up 0 = link is down 1 = jabber detected 0 = jabber not detected. Default is low 1 = supports extended capabilities registers Assigned to the 3rd through 18th bits of the organizationally unique identifier (OUI). Micrel's OUI is 0010A1 (hex). Assigned to the 19th through 24th bits of the organizationally unique identifier (OUI). Micrel's OUI is 0010A1 (hex). Six bit manufacturer's model number Four bit manufacturer's model number 1 = next page capable 0 = no next page capability 1 = remote fault supported 0 = no remote fault 1 = pause function supported 0 = no pause function 1 = T4 capable 0 = no T4 capability 1 = TX with full-duplex 0 = no TX full-duplex capability 1 = TX capable 0 = no TX capability 1 = 10Mbps with full-duplex 0 = no 10Mbps full-duplex capability Description 1 = capable of 100BASE-X half-duplex 0 = not capable of 100BASE-X half-duplex 1 = 10Mbps with full-duplex 0 = no 10Mbps with full-duplex capability 1 = 10Mbps with half-duplex 0 = no 10Mbps with half-duplex capability
KS8721BL/SL
Default(1) RO RO RO RO RO RO RO/LH RO RO/LL RO/LH RO RO Mode 1 1 1 0 1 0 0 1 0 0 1 0022h
Register 2h - PHY Identifier 1
Register 3h - PHY Identifier 2 3.15:0 PHY ID Number RO 000101
3.9:4 3.3:0 4.15 4.14 4.13 4.12:11 4.10 4.9 4.8
Model Number Revision Number Next Page Reserved Remote Fault Reserved Pause 100BASE-T4 100BASE-TX Full-Duplex
RO RO RW RO RW RO RW RO RW
100001 1001 0 0 0 0 0 0 Set by SPD100 & DUPLEX Set by SPD100 Set by DUPLEX
Register 4h - Auto-Negotiation Advertisement
4.7 4.6
100BASE-TX 10BASE-T Full-Duplex
RW RW
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Address 4.5 4.4:0 5.15 5.14 5.13 5.12 5.11:10 Name 10BASE-T Selector Field Next Page Acknowledge Remote Fault Reserved Pause 5.10 5 .11 0 0 No PAUSE 0 1 Asymmetric PAUSE (link partner) 1 0 Symmetric PAUSE 1 1 Symmetric & Asymmetric PAUSE (local device) 1 = T4 capable 0 = no T4 capability 1 = TX with full-duplex 0 = no TX full-duplex capability 1 = TX capable 0 = no TX capability 1 = 10Mbps with full-duplex 0 = no 10Mbps full-duplex capability 1 = 10Mbps capable 0 = no 10Mbps capability [00001] = IEEE 802.3 Description 1 = 10Mbps capable 0 = no 10Mbps capability [00001] = IEEE 802.3 1 = next page capable 0 = no next page capability 1 = link code word received from partner 0 = link code word not yet received 1 = remote fault detected; 0 = no remote fault
KS8721BL/SL
Default(1) RW RW RO RO RO RO RO Mode 1 00001 0 0 0 0 0
Register 5h - Auto-Negotiation Link Partner Ability
5.9 5.8 5.7 5.6 5.5 5.4:0 6.15:5 6.4 6.3 6.2 6.1 6.0
100 BASE-T4 100BASE-TX Full-Duplex 100BASE-TX 10BASE-T Full-Duplex 10BASE-T Selector Field Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner Auto-Negotiation Able Next Page Reserved Message Page
RO RO RO RO RO RO RO
0 0 0 0 0 00001 0 0 0 1 0 0
Register 6h - Auto-Negotiation Expansion 1 = fault detected by parallel detection 0 = no fault detected by parallel detection 1 = link partner has next page capability 0 = link partner does not have next page capability 1 = local device has next page capability 0 = local device does not have next page capability 1 = new page received 0 = new page not yet received 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability 1 = additional next page(s) will follow 0 = last page 1 = message page 0 = unformatted page RO/LH RO RO RO/LH RO
Register 7h - Auto-Negotiation Next Page 7.15 7.14 7.13 RW RO RW 0 0 1
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Address 7.12 7.11 Name Acknowledge 2 Toggle Description 1 = will comply with message 0 = cannot comply with message 1 = previous value of the transmitted link code word equaled logic One 0 = logic Zero 11-bit wide field to encode 2048 messages 1 = additional next page(s) will follow 0 = last page 1 = successful receipt of link word 0 = no successful receipt of link word 1 = Message Page 0 = unformatted page 1 = able to act on the information 0 = not able to act on the information 1 = previous value of transmitted link code word equal to logic zero 0 = previous value of transmitted link code word equal to logic one
KS8721BL/SL
Default(1) RW RO Mode 0 0
7.10:0 8.15 8.14 8.13 8.12 8.11
Message Field Next Page Acknowledge Message Page Acknowledge 2 Toggle
RW RO RO RO RO RO
001 0 0 0 0 0
Register 8h - Link Partner Next Page Ability
8.10:0 15.15:0 1b.15 1b.14 1b.13 1b.12 1b.11 1b.10 1b.9 1b.8 1b.7 1b.6 1b.5 1b.4
Message Field RXER Counter Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Enable Remote Fault Interrupt Enable Link Up Interrupt Enable Jabber Interrupt Receive Error Interrupt Page Receive Interrupt Parallel Detect Fault Interrupt RX Error counter for the RX_ER in each package 1 = Enable jabber interrupt 0 = Disable jabber interrupt 1 = Enable receive error interrupt 0 = Disable receive error interrupt 1 = Enable page received interrupt 0 = Disable page received interrupt 1 = Enable parallel detect fault interrupt 0 = Disable parallel detect fault interrupt 1 = Enable link partner acknowledge interrupt 0 = Disable link partner acknowledge interrupt 1 = Enable link down interrupt 0 = Disable link down interrupt 1 = Enable remote fault interrupt 0 = Disable remote fault interrupt 1 = Enable link up interrupt 0 = Disable link up interrupt 1 = Jabber interrupt occurred 0 = Jabber interrupt has not occurred 1 = Receive error occurred 0 = Receive error has not occurred 1 = Page receive occurred 0 = Page receive has not occurred 1 = Parallel detect fault occurred 0 = Parallel detect fault has not occurred
RO RO RW RW RW RW RW RW RW RW RO/SC RO/SC RO/SC RO/SC
0 000 0 0 0 0 0 0 0 0 0 0 0 0
Register 15h - RXER Counter
Register 1bh - Interrupt Control/Status Register
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Address 1b.3 1b.2 1b.1 1b.0 Name Link Partner Acknowledge Interrupt Link Down Interrupt Remote Fault Interrupt Link Up Interrupt Description 1 = Link partner acknowledge occurred 0 = Link partner acknowledge has not occurred 1 = Link down occurred 0 = Link down has not occurred 1 = Remote fault occurred 0 = Remote fault has not occurred 1 = Link up interrupt occurred 0 = Link up interrupt has not occurred
KS8721BL/SL
Default(1) RO/SC RO/SC RO/SC RO/SC Mode 0 0 0 0
Register 1fh - 100BASE-TX PHY Controller 1f.15:14 1f.13 1f.12 1f.11 Reserved Pairswap Disable Energy Detect Force Link 1 = Disable MDI/MDI-X 0 = Enable MDI/MDI-X 1 = Presence of signal on RX+/RX- analog wire pair 0 = No signal detected on RX+/RX1 = Force link pass 0 = Normal link operation This bit bypasses the control logic and allow transmitter to send pattern even if there is no link. 1 = Enable power-saving 0 = Disable 1 = Interrupt pin active high 0 = Active low 1 = Enable jabber counter 0 = Disable 1 = Auto-negotiation complete 0 = Not complete 1 = Flow control capable 0 = No flow control 1 = PHY in isolate mode 0 = Not isolated [000] = Still in auto-negotiation [001] = 10BASE-T half-duplex [010] = 100BASE-TX half-duplex [011] = Reserved [101] = 10BASE-T full-duplex [110] = 100BASE-TX full-duplex [111] = PHY/MII isolate 1 = Enable SQE test 0 = Disable 1 = Disable scrambler 0 = Enable RO RW RO RW 0 0 0 0
1f.10 1f.9 1f.8 1f.7 1f.6 1f.5 1f.4:2
Power-Saving Interrupt Level Enable Jabber Auto-Negotiation Complete Enable Pause (Flow-Control Result) PHY Isolate Operation Mode Indication
RW RW RW RW RO RO RO
1 0 1 0 0 0 0
1f.1 1f.0
Note:
Enable SQE Test Disable Data Scrambling
RW RW
0 0
1.
RW = Read/Write. RO = Read Only. SC = Self Clear. LH = Latch High. LL = Latch Low.
Some of the default values are set by strap-in. See "Strapping Options."
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Absolute Maximum Ratings(1)
Storage Temperature (Ts) .........................-55C to +150C Supply Referenced to GND.......................... -0.5V to +4.0V All Pins ......................................................... -0.5V to +4.0V
Operating Ratings(2)
Supply Voltage (VDD_PLL, VDD_TX, VDD_RXC, VDD_RCV, VDDC) ......... +2.5V (VDDIO) .............................................................. +3.3V Ambient Temperature (TA) Commercial ......................................... 0C to +70C Industrial .......................................... -40C to +85C Package Thermal Resistance(3) LQFP(JA) No Airflow ........................................... 83.56C/W SSOP(JA) No Airflow ........................................... 75.19C/W
Electrical Characteristics(4)
VDD = 3.3V 10%
Symbol IDD1 IDD2 IDD3 IDD5 TTL Inputs VIH VIL IIN VOH VOL IOZ RIN Input High Voltage Input Low Voltage Input Current Output High Voltage Output Low Voltage Output Tri-state Leakage RX+/RX- Differential Input Resistance Propagation Delay VO VIMB tr, tf Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET Propagation Delay Jitters from TDTX to magentics 0.75 45 0.7 60 1.4 from magnetics to RDTX 50 from each output to VDD 50 from each output to VDD 3 0 0.95 8 50 110 1.05 2 5 0.5 0.5 5 VIN = GND ~ VDDIO IOH = -4mA IOL = 4mA -10 1/2VDD(I/O) +0.6 0.4 10 1/2VDD(I/O) +0.2 0.8 10 V V A V V A k ns V % ns ns ns % V ns ns(pp) Parameter Normal 100BASE-TX Normal 100BASE-TX (Independent of utilization) Power Saving Mode 1 Power Down Mode Condition Including 43mA output current Including 103mA output current Auto-negotiation is Enable Min Typ 116 151 47 4 Max Units mA mA mA mA Total Supply Current (including TX output driver current)(5)
TTL Outputs
100Base-TX Receive
10Base-TX Transmit (measured differentially after 1:1 transformer)
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10Base-TX Receive RIN VSQ VP tr, tf X1, X2 RXC100 RXC10 TXC100 TXC10
Notes:
KS8721BL/SL
RX+/RX- Differential Input Resistance Squelch Threshold Peak Differential Output Voltage Jitters Added Rise/Fall Time Crystal Oscillator Receive Clock, 100TX Receive Clock, 10T Receive Clock Jitters Transmit Clock, 100TX Transmit Clock, 10T Transmit Clock Jitters 5MHz square wave 50W from each output to VDD 50W from each output to VDD 2.2
8 400 2.8 3.5 25 25 25 2.5 3.0 25 2.5 1.8
kW mV V ns ns MHz MHz MHz ns(pp) MHz MHz ns(pp)
10Base-TX Transmit (measured differentially after 1:1 transformer)
Clock Outputs
1. Exceeding the absolute maximum rating may damage the device. Operating at maximum conditions for extended periods may affect device reliability. 2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD) 3. No (HS) heat spreader in this package. 4. Specification for packaged product only. 5. There is 100% data transmission in full-duplex mode and a minimum IPG with a 130-meter cable.
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Timing Diagrams
Figure 4. 10BASE-T MII Transmit Timing
Symbol tSU1 tSU2 tHD1 tHD2 tCRS1 tCRS2 tLAT tSQE tSQEP
Parameter TXD [3:0] Set-Up to TXC High TXEN Set-Up to TXC High TXD [3:0] Hold After TXC High TXEN Hold After TXC High TXEN High to CRS Asserted Latency TXEN Low to CRS De-Asserted Latency TXEN High to TXP/TXM Output (TX Latency) COL (SQE) Delay After TXEN De-Asserted COL (SQE) Pulse Duration
Min 10 10 0 0
Typ
Max
Units ns ns ns ns
4 8 4 2.5 1.0
BT(1) BT BT s s
Table 3. 10BASE-T MII Transmit Timing Parameters
Note: 1. 1BT = 10ns at 10BASE-TX
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Figure 5. 100BASE-T MII Transmit Timing
Symbol tSU1 tSU2 tHD1 tHD2 tHD3 tCRS1 tCRS2 tLAT
Parameter TXD [3:0] Set-Up to TXC High TXEN Set-Up to TXC High TXD [3:0] Hold After TXC High TXER Hold After TXC High TXEN Hold After TXC High TXEN High to CRS Asserted Latency TXEN Low to CRS De-Asserted Latency TXEN High to TXP/TXM Output (TX Latency)
Min 10 10 0 0 0
Typ
Max
Units ns ns ns ns ns
4 4 9
BT(1) BT BT
Table 4. 100BASE-T MII Transmit Timing Parameters
Note: 1. 1BT = 10ns at 100BASE-TX
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Start of Stream
End of Stream
Figure 6. 100BASE-T MII Receive Timing
Symbol tP tWL tWH tSU tHD tRLAT tCRS1 t CRS2
Parameter RXC Period RXC Pulse Width RXC Pulse Width RXD [3:0], RXER, RXDV Set-Up to Rising Edge of RXC RXD [3:0], RXER, RXDV Hold from Rising Edge of RXC CRS to RXD Latency, 4B or 5B Aligned "Start of Stream" to CSR Asserted "End of Stream" to CSR De-Asserted
Min 20 20
Typ 40
Max
Units ns ns ns
20 20 6 106 154 138 186
ns ns BT ns ns
Table 5. 100BASE-T MII Receive Timing Parameters
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Figure 7. Auto-Negotiation/Fast Link Pulse Timing
Symbol tBTB tFLPW tPW tCTD tCTC
Parameter FLP Burst to FLP Burst FLP Burst Width Clock/Data Pulse Width Clock Pulse to Data Pulse Clock Pulse to Clock Pulse Number of Clock/Data Pulses per Burst
Min 8
Typ 16 2 100 69 136
Max 24
Units ms ms ns s s s
17
33
Table 6. Auto-Negotiation/Fast Link Pulse Timing Parameters
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Figure 8. Serial Management Interface Timing
Symbol tP tMD1 tMD2 tMD3
Parameter MDC Period MDIO Set-Up to MDC (MDIO as Input) MDIO Hold After MDC (MDIO as Input) MDC to MDIO Valid (MDIO as Output)
Min 10 10
Typ 400
Max
Units ns ns ns
222
ns
Table 7. Serial Management Interface Timing Parameters
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Figure 9. Reset Timing
Symbol tsr
Parameter Stable Supply Voltages to Reset High Table 8. Reset Timing Parameters
Min 50
Typ
Max
Units s
Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 10 when powering up the KS8721BL/SL device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 11.
VCC
D1 KS8721BL/SL RST C 10F
R 10k
CPU/FPGA RST_OUT_n D2 D1, D2: 1N4148
Figure 10. Recommended Reset Circuit
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VCC D1: 1N4148 D1 KS8721BL/SL RST C 10F R 10k
KS8721BL/SL
Figure 11. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. Reference Circuit for Strapping Option Configuration Figure 12 shows the reference circuit for strapping option pins.
3.3V
Pull-Up
LED pin
KS8721BL/SL
3.3V
Pull-down
LED pin
KS8721BL/SL
Reference circuits for unmanaged programming through LED ports.
Figure 12. Reference Circuit, Strapping Option Pins
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Selection of Isolation Transformers(1)
One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics.
Parameter Turns ratio Open-circuit inductance (min) Leakage inductance (max) Inter-winding capacitance (max) D.C. resistance (max) Insertion loss (max) HIPOT (min)
Note:
Value 1 CT : 1 CT 350H 0.4H 12pF 0.9 1.0dB 1500Vrms
Test Condition 100mV, 100kHz, 8mA 1MHz (min)
0MHz - 65MHz
1.
The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can be compensated or by increasing the line drive current by means of reducing the ISET resistor value. Please select the transformer that supports auto-MDI/MDI-X.
Selection of Reference Crystal
An oscillator or crystal with the following typical characteristics is recommended.
Characteristics Frequency Frequency tolerance (max) Load capacitance (max) Series resistance (max) Value 25
100
Units MHz ppm pF
20 40
Single Port Magnetic Manufacturer Pulse Bel Fuse YCL Transpower Delta LanKom Integrated Transformers Pulse Pulse
Part Number H1102 S558-5999-U7 PT163020 HB726 LF8505 LF-H41S J0011D21 J00-0061 Table 9. Qualified Transformer Lists
Auto MDIX Yes Yes Yes Yes Yes Yes Yes Yes
Number of Ports 1 1 1 1 1 1 1 1
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Package Information
48-Pin SSOP (SM)
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KS8721BL/SL
48-Pin LQFP (LQ)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2004 Micrel, Incorporated.
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